The present invention relates to semi-conductor integrated circuits of the type comprising configurable logic circuit arrays.
The invention is a development of the configurable logic circuit arrays disclosed in our British Patent Specification No. 2180382 (having a corresponding U.S. Pat. No. 4,935,734) and U.S. Pat. No. 5,001,368. In the former, the logic circuit array comprises a matrix of discrete sites or cells at each of which is a logic circuit which is adapted to perform a simple logic function. Typically the simple logic function is implemented by means of a two input NAND gate. As made each logic circuit has what may be referred to as a restricted signal translation system by which each logic circuit has selectable direct connection paths to only a few of the other logic circuits. More particularly each direct connection path which is selectable as to its conduction state, extends, for each said logic circuit, from its output to inputs of a first set of some of other said logic circuits and from its inputs to outputs of a second set of some of other said logic circuits, all of the sets (for all of the logic circuits) each being unique. Such a restricted signal translation system provides what can be conveniently referred to as local direct connection paths.
An array of this type is capable of being programmed in such a manner as to configure the various NAND gates, as required, to perform various and different logic functions. One such function is known as a latching function and in the logic array as disclosed in Specification No. 2180382, a latching function may be implemented using four NAND gates. This has the disadvantage that the greater the number of latching functions that may be required from any logic array, the fewer NAND gates remain for other required functions. This has the effect of reducing the overall effectiveness of the array.
The invention of U.S. Pat. No. 5,001,368 overcomes this disadvantage by providing an additional logic circuit for inclusion in each of the logic circuits at each discrete site to enable each site to have a greater programmable facility and thereby increase the overall utilisation of the array. As with GB 2180382 the site/cell of each logic circuit has the aforesaid restricted signal translation system. Each additional logic circuit is arranged within the logic circuit of the site or cell to be selectively controlled by control means to cause each logic circuit and additional logic circuit comprising each cell to operate as either a first or a second different simple logic function. More particularly, each cell is constructed to operate as a NAND gate or as a latch circuit function.
Providing such local direct connection paths between physically neighbouring logic circuit sites facilitates the establishment of a desired particular circuit function in a localised configuration of logic circuits, ie. in part only of the chip area occupied by an appropriate number of discrete sites of the logic circuits and by the direct connection paths. Interconnections between such localised configurations for overall circuit/system requirements can be either simply by said direct connection paths or by a further signal translation system by way of a direct connection bus directly connected to the logic circuits and extending throughout the array--for example as a series of rows and columns. Such connections might conveniently be referred to as global connections.
The so-called local direct connections and global connections constitute routing resources which are used to connect to discretely programmed logic functions. These resources can be combined by routing through a cell in order to complete the connection between functions. Once a logic circuit has been used in this matter to complete the routing that logic circuit can no longer be used for function. This reduces the overall effectiveness of the array. An object of one aspect of this invention is to overcome this disadvantage by providing additional connection resources in an arrangement not previously contemplated.
A feature of the afore-described configurable logic arrays is that each discrete site or cell is identical thus in the case of GB 2180382 each discrete site comprises a NAND gate whilst in the case of U.S. Pat. No. 5,001,368 each discrete cell comprises a NAND gate and an additional logic circuit which enables the cell to function exclusive as a NAND gate or exclusively as a latch circuit function Implementing other circuit functions (be they logic functions or otherwise) requires the various cells to be configured as required to perform various and different circuit functions Other functions frequently required are XOR and D-flip-flop. Again this has the disadvantage that the greater number of these functions that may be required from any logic array the fewer gates remain for other required functions which has the effect of reducing the overall effectiveness of the array